SSD3030P p-channel enhancement mode mosfet product summary v ds (v ) i d (a ) -30v -30a r ds(on ) (m ? ) max 25 @v gs = -10v 45 @v gs = -5 v south sea semiconductor reserves the right to make changes to improve reliability or manufacturability without advance notice. south sea semiconducto r, j anuary 2008 (rev 2.1 ) 1 absolute maximum r at ings (t a = 25 c unless otherwise noted) therma l characteristics parameter symbol limi t uni t o drain-source vo ltage gate-source vo ltage drain current-continuous @ t j = 125 c -pulsed drain-source diode forward current maximum power dissipation operating junction and storage t emperature range o a a b v ds v gs i d i dm i s p d t j , t stg -3 0 v v a a a w c o 25 - + -3 0 -6 0 -1.7 50 -55 to 150 to -252 d g s fe at ures super high density cell design for low r ds(on ) . rugged and reliable. to -252 package. d g s a r ja c/ w o 50 thermal resistance, junction-to-ambient thermal resistance, junction-to-case r jc 3 55 @v gs = -4.5 v pb free.
SSD3030P south sea semiconductor reserves the right to make changes to improve reliability or manufacturability without advance notice. south sea semiconductor , january 2008 (rev 2.1 ) 2 p-channel electrical characteristics (t a = 25 c unless otherwise noted) o unit symbol parameter condition mi n ty p ma x c zero gate v oltage drain current drain-source breakdown vo ltage gate-body leakage gate threshold vo ltage drain-source on-state resistanc e bv dss i dss i gs s v gs(th) r ds(on ) v gs =0v , i d =-250 a v ds =-24v , v gs =0v v gs = 25v , v ds =0v v ds =v gs i d =-250 a v gs =-10v , i d =-20a v gs = - 5v , i d = -10a m v v a na -3 0 -1 100 -2.5 2 5 45 -1 on-state drain current forward t ransconductance tu rn-on delay ti me rise t im e tu rn-of f delay t im e fall ti me i d(on ) g fs t d(on ) t r t d(off) t f v ds =-5v , v gs =-10v v ds =-5v , i d =-5.3a v dd =-15 v, v ge n =-10 v, -4 0 15 17. 4 169 95. 4 17. 6 ns p f s a input capacitanc e output capacitanc e reverse tr ansfer capacitance c is s c os s c rss v ds =-15v v gs =0v f=1.0mhz 1000 200 110 to tal gate charge q g v ds =-15v , i d = - 8a, v gs = -10v 2 0 i d =-1a, r ge n =6 , diode forward v oltage v sd v gs =0v , i d = -1 a v -0.7 5 -1.2 gate-source charge gate-drain charge q gs q gd i d = -6a, 3. 5 6 v gs = -10v nc -1.9 v ds = -15v , v ds =-15v , i d = - 8a, v gs = -4.5 v 11 notes a. surface mounted on fr4 board, t <10 sec. b. pulse t est pulse width < 300 s, duty cycle < 2%. c. guaranteed by design, not subject to production testing. - - - v gs =-4.5v , i d =-10a 55 1200 150 2 5
SSD3030P south sea semiconductor reserves the right to make changes to improve reliability or manufacturability without advance notice. south sea semiconductor , january 2008 (rev 2.1 ) 3 v b s s d d e z i l a m r o n , g a t l o v n w o d k a e r b e c r u o s - n i a r d e figure 6. breakdown v oltage v ariation with t emperature tj , junction te mperature ( c ) o -50 -25 0 25 50 75 100 125 1.15 1.10 1.05 1.00 0.95 0.90 0.85 i d = -250 a -v ds , drain-to-source vo ltage (v ) i - d ) a ( t n e r r u c n i a r d , figure 1. output characteristics 0 2 4 6 8 10 1 2 10 8 6 4 2 0 -v gs = 3v -v gs = 4v -v gs = 10, 9, 8, 7, 6, 5 v -v gs , gate-to-source vo ltage (v ) i - d u c n i a r d , ) a ( t n e r r figure 2. transfer characteristics 0 0.6 1.0 1.4 1.8 2.2 2.6 2 5 2 0 15 1 0 5 0 - 5 5 c o 25 c tj = 125 c o o -v ds , drain-to-source vo ltage (v ) ) f p ( e c n a t i c a p a c , c figure 3. capacitance 0 5 10 15 20 25 3 0 c i s s c o s s c r s s 1200 0 1000 800 600 400 200 r , ) n o ( s d e c n a t s i s e r - n o ( d e z i l a m r o n ) -55 -25 0 25 50 75 100 12 5 1. 8 1. 6 1. 4 1.2 1.0 0.8 0. 6 figure 4. on-resistance v ariation with t emperature v gs = -10v t j , junction te mpertature ( c ) o i d = -8 a d e z i l a m r o n , h t v e g a t l o v d l o h s e r h t e c r u o s - e t a g tj , junction te mperature ( c ) figure 5. gate threshold v ariation with t emperature o -50 -25 0 25 50 75 100 125 v ds = v gs i d = -250 a 1. 3 1. 2 1. 1 1. 0 0. 9 0. 8 0. 7 0.6
SSD3030P south sea semiconductor reserves the right to make changes to improve reliability or manufacturability without advance notice. south sea semiconductor , january 2008 (rev 2.1 ) 4 -i ds , drain-source current (a ) g , s f ) s ( e c n a t c u d n o c s n a r t 0 5 10 15 2 0 figure 7. t ransconductance va riation with drain current i - s ) a ( t n e r r u c n i a r d - e c r u o s , 20. 0 -v sd , body diode forward vo ltage (v ) figure 8. body diode forward vo ltage v ariation with source current 0.2 0.4 0.6 0.8 1.0 1.2 v - s g ) v ( e g a t l o v e c r u o s o t e t a g , figure 9. gate charge qg , t otal gate charge (nc) 0 3 6 9 12 15 18 21 2 4 10 8 6 4 2 0 v ds = -15v i d = -8 a - i d ) a ( t n e r r u c n i a r d , -v sd , drain-to-source vo ltage (v ) figure 10. maximum safe operating a rea 2 0 1 6 1 2 8 4 0 10. 0 1.0 v gs = 0 v v ds = -15v 0.01 0.10 1.00 10.00 100.00 100 10 0.1 0.0 1 1 dc 1 100m s r ds(on) l imit v gs = 10v single pulse r ja = 9 6 o c/ w t a = 2 5 o c 10m s 1m s 100 s 10 s
SSD3030P south sea semiconductor reserves the right to make changes to improve reliability or manufacturability without advance notice. south sea semiconductor , january 2008 (rev 2.1 ) 5 figure 1 1. switching t est circuit v gs r gen v ou t v dd v in d r l g s figure 12. switching w aveforms inver ted pulse widt h t r t d(on ) v ou t v in t on t of f t d(of f) t f 10% 50% 50% 90% 10% 90% 10% 90% figure 13. normalized thermal t ransient impedance curve r e v i t c e f f e d e z i l a m r o n , ) t ( e c n a d e p m i l a m r e h t t n e i s n a r t square w ave pulse duration (sec) 0.00 1 0.01 0. 1 1 0.001 0.01 0. 1 1 10 100 1000 r ja (t) = r(t) * r ja r ja = 96 c/w t j - t a = p * r ja (t ) duty cycle, d = t 1 / t 2 p(pk ) t 1 t 2 single pulse 0.01 0.02 0.05 0. 1 0. 2 d = 0. 5
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